Integrated circuits of microelectronic devices include interconnects to wire together the devices, thus making the circuits. In a typical process for making the interconnects, a first interconnect 100 is embedded in first dielectric material 110 and covered by a stack of dielectric material 120. Above the dielectric stack 120 is a hard mask 130 to aid in forming an opening 140 in the dielectric stack 120 which reaches the first interconnect 100. After the opening 140 is formed, the hard mask 130 is removed with a wet etch which also corrodes/etches 150 a portion of the first interconnect 100. The corrosion/etching 150 of the first interconnect 100 may extend such that it undercuts 153 the dielectric stack 120. In addition, if the opening is misaligned (see FIG. 1), the etch of dielectric stack 120 to form opening 140, and/or hard mask removal wet etch can also over-etch 155 a portion of the first dielectric material 110. In either case, the corrosion/etching of the first interconnect, and the etching of the first dielectric material causes device reliability concerns. Thus, an improved method and structure for forming interconnects with minimal corrosion/over-etching is needed. The need is especially acute for copper-ultra low k interconnect wiring structures.